The present invention relates to an input/output circuit, and more particularly, to an input/output circuit of a field effect semiconductor integrated circuit, for inputting/outputting signals from/to the outside of the semiconductor integrated circuit.
With the recent high integration of semiconductor devices, high performance has been increasingly demanded in the technology of input/output circuits for inputting/outputting signals from/to the outside of the devices. In particular, while the voltage of external input/output signals remains at the conventional TTL level, the supply voltage internal to a semiconductor integrated circuit is required to be lower as the size of the semiconductor integrated circuit is made finer. In view of this, it is required to provide an input/output circuit capable of accepting a voltage higher than the supply voltage internal to a semiconductor integrated circuit. In realization of such an input/output circuit, a problem arises in a p-channel transistor of the output part of the input/output circuit. That is, in a normal configuration, the supply voltage is applied to an n-well region of the p-channel transistor of the output part. The drain of the p-channel transistor is a p-type diffusion region. Therefore, when a voltage higher than the supply voltage is applied to the drain, a forward bias is applied to the PN junction causing flow of a large current, and this may possibly destroy the semiconductor integrated circuit. Thus, a unique construction is necessary for an input/output circuit capable of accepting a voltage higher than the supply voltage internal to the semiconductor integrated circuit.
FIG. 11 illustrates an input/output circuit capable of accepting a voltage higher than the supply voltage internal to the semiconductor integrated circuit, as first related art. In FIG. 11, for simplification of description, only a p-channel transistor B02 of an output part is shown, omitting an input part and an n-channel transistor of the output part. The p-channel transistor B02 includes a source diffusion region B02a, a gate B02b, a drain diffusion region B02c, an n-well diffusion region B02d, a substrate B02e and device isolators B02g and B02h. The input/output of signals into/from a semiconductor integrated circuit having the input/output circuit shown in FIG. 11 is entirely performed via an input/output pad B03. The supply voltage VDD (V) is applied to the source diffusion region B02a. Therefore, in the initial state, the voltage at the n-well diffusion region B02d is as high as VDD (V) due to the PN junction with the source diffusion region B02a. 
The operation of the input/output circuit with the above configuration is as follows. Herein, the case that a voltage is applied from outside when the input/output circuit is in the input state is described. When an input at a voltage VH (V) higher than the supply voltage is applied to the input/output pad B03, the potential at the n-well diffusion region B02d rises to as high as VH (V) due to the PN junction with the drain diffusion region B02c. A current flows into the input/output pad B03 during the charging of the n-well diffusion region B02d to VH (V). However, the current flow stops once the voltage at the n-well diffusion region B02d reaches VH (V). Also, at this time, a reverse voltage is applied to the PN junction between the n-well diffusion region B02d and the source diffusion region B02a. Therefore, no large current will flow between the n-well diffusion region B02d and the source diffusion region B02a. Accordingly, using the input/output circuit shown in FIG. 11, the semiconductor integrated circuit is prevented from destruction even when a voltage higher than the supply voltage internal to the semiconductor integrated circuit is input into the semiconductor integrated circuit.
The input/output circuit shown in FIG. 11 does not accept a voltage lower than the ground voltage due to the existence of the n-channel transistor (not shown) of the output part. An input/output circuit capable of accepting a voltage lower than the ground voltage is realized by a diffusion method separating a p-well. FIG. 12 illustrates a conventional input/output circuit capable of accepting a voltage lower than the ground voltage, as second related art. In FIG. 12, for simplification of description, only an n-channel transistor C02 of an output part is shown, omitting an input part and a p-channel transistor of the output part. The n-channel transistor C02 includes a source diffusion region C02a, a gate C02b, a drain diffusion region C02c, a p-well diffusion region C02d, a substrate C02e and device isolators C02g and C02h. The input/output of signals into/from a semiconductor integrated circuit (LSI) having the input/output circuit shown in FIG. 12 is entirely performed via an input/output pad C03. The source diffusion region C02a is grounded. Therefore, in the initial state, the potential at the p-well diffusion region C02d is as low as the ground voltage due to the PN junction with the source diffusion region C02a. 
The operation of the input/output circuit with the above configuration is as follows. Herein, the case that a voltage is applied from outside when the input/output circuit is in the input state is described. When an input signal at a voltage VL (V) lower than the ground voltage is applied to the input/output pad C03, the voltage at the p-well diffusion region C02d drops to as low as VL (V) due to the PN junction with the drain diffusion region C02c. A current flows from the input/output pad C03 during the discharging of the p-well diffusion region C02d to VL (V). However, the current flow stops once the potential at the p-well diffusion region C02d reaches VL (V). Also, at this time, a reverse voltage is applied to the PN junction between the p-well diffusion region C02d and the source diffusion region C02a. Therefore, no large current will flow between the p-well diffusion region C02d and the source diffusion region C02a. Accordingly, using the conventional input/output circuit shown in FIG. 12, the LSI is prevented from destruction even when a voltage lower than the ground voltage is input into the LSI.
However, the related art described above has the following problems. In the input/output circuit shown in FIG. 11, after a voltage higher than the supply voltage is applied during input, the potential at the n-well diffusion region B02d of the p-channel transistor B02 is higher than the supply voltage during output. This deteriorates the current flow capability due to a back bias effect.
In the input/output circuit shown in FIG. 12, after a voltage lower than the ground voltage is applied during input, the potential at the p-well diffusion region C02d of the n-channel transistor C02 is lower than the ground voltage during output. This deteriorates the current flow capability due to the back bias effect.
An object of the present invention is providing an input/output circuit capable of preventing deterioration in current flow capability due to the back bias effect.
According to one aspect of the present invention, the input/output circuit is an input/output circuit of a semiconductor integrated circuit, including a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit draws a charge from an n-well diffusion region of the first p-channel transistor.
According to another aspect of the invention, the input/output circuit is an input/output circuit of a semiconductor integrated circuit, including a first n-channel transistor and a charge drawing circuit. The first n-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit draws a charge from a p-well diffusion region of the first n-channel transistor.
The input/output circuit described above includes the charge drawing circuit. Therefore, deterioration in current flow capability due to the back bias effect is prevented.
According to yet another aspect of the invention, the input/output circuit is an input/output circuit for outputting a signal from an internal circuit of a semiconductor integrated circuit to an input/output pad of the semiconductor integrated circuit, including a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected between a power supply node receiving a supply voltage internal to the semiconductor integrated circuit and the input/output pad. The gate of the first p-channel transistor receives a signal from an internal circuit of the semiconductor integrated circuit directly or indirectly. The charge drawing circuit draws a charge from an n-well diffusion region of the first p-channel transistor to a ground node receiving a ground voltage when the input/output circuit outputs the signal from the internal circuit to the input/output pad.
Preferably, the charge drawing circuit includes a first n-channel transistor and a second n-channel transistor. The first n-channel transistor is connected between the n-well diffusion region of the first p-channel transistor and a first node, and is turned ON when the input/output circuit outputs the signal from the internal circuit to the input/output pad. The second n-channel transistor is connected between the first node and the ground node, and is turned OFF when the input/output circuit outputs the signal from the internal circuit to the input/output pad.
In the input/output circuit described above, the potential at the n-well diffusion region of the first p-channel transistor is kept at the internal supply voltage level when the input/output circuit outputs the signal from the internal circuit to the input/output pad. Therefore, deterioration in current flow capability due to the back bias effect of the first p-channel transistor is prevented.
According to still another aspect of the invention, the input/output circuit is an input/output circuit for outputting a signal from an internal circuit of a semiconductor integrated circuit to an input/output pad of the semiconductor integrated circuit, including a first n-channel transistor and a charge drawing circuit. The first n-channel transistor is connected between a ground node receiving a ground voltage and the input/output pad. The gate of the first n-channel transistor receives a signal from an internal circuit of the semiconductor integrated circuit directly or indirectly. The charge drawing circuit draws a charge from a p-well diffusion region of the first n-channel transistor to a power supply node receiving a supply voltage internal to the semiconductor integrated circuit when the input/output circuit outputs the signal from the internal circuit to the input/output pad.
Preferably, the charge drawing circuit includes a first p-channel transistor and a second p-channel transistor. The first p-channel transistor is connected between the p-well diffusion region of the first n-channel transistor and a first node, and is turned ON when the input/output circuit outputs the signal from the internal circuit to the input/output pad. The second p-channel transistor is connected between the first node and the power supply node, and is turned OFF when the input/output circuit outputs the signal from the internal circuit to the input/output pad.
In the input/output circuit described above, the potential at the p-well diffusion region of the first n-channel transistor is kept at the ground voltage level when the input/output circuit outputs the signal from the internal circuit to the input/output pad. Therefore, deterioration in current flow capability due to the back bias effect of the first n-channel transistor is prevented.